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GET2CHIP SUPPORTS SUPERLOG™ FOR NEXT-GENERATION SOC DESIGN TOOLS
Architectural Synthesis Leader Takes SUPERLOG Into Silicon
San Jose, Calif. - January 22, 2001 - Get2Chip.com, Inc., an emerging technology leader in chip design solutions and provider of the first viable architectural synthesis solution for system-on-chip (SOC) ultra-deep sub-micron designs, today announced its support for the SUPERLOG™ design language, developed by Co-Design Automation, Inc.
The dramatic growth in complexity of SOC designs makes the register transfer level (RTL) design methodology slow and tedious. This issue requires a paradigm shift in order to enable chip designers to be competitive and meet design goals.
In an RTL synthesis-based methodology, the designer explicitly specifies the operations to be performed in every clock cycle and manually infers the registers in the design. Architectural synthesis on the other hand, enables designs to be completed at a higher level of abstraction by allowing the designer to automatically generate different micro-architectures based on timing, area and clock latency constraints.
SUPERLOG allows designers to model digital systems at a higher level of abstraction. When combined with architectural synthesis, this capability allows an implementation path from high abstraction level design to gates. SUPERLOG supports new functionality and constructs, which promote the methodology for designing at the architectural level, both for implementation and verification. Features such as sequential assertions for protocol checking and virtual interfaces allow interface constraints for architectural synthesis to be embedded in the design specification. These features also support a verification methodology across architectural and RTL implementation levels.
"VOLARE, our architectural synthesis solution which is completely integrated with our high-capacity logic synthesis and static timing analysis capability, will support and drive an implementation path for SUPERLOG down to silicon," said Bernd Braune, chairman, president and CEO of Get2Chip.
"Get2Chip has been proactive in working with different language groups and committees to drive the evolution of hardware design language capabilities for implementation. We have been part of the team driving SUPERLOG and have actively provided feedback to the SUPERLOG team in defining modeling capabilities for building a smooth and efficient design flow from the architectural to the gate-level."
"SUPERLOG is gathering a high degree of momentum across the electronics industry, and its inclusion in Get2Chip's technically-advanced VOLARE synthesis product is an indicator of the productivity enhancement it can provide throughout the design flow," noted Simon Davidmann, president and CEO of Co-Design Automation.
"We chose to work with Get2Chip because they have shown consistently better results in taking a high level design description through to silicon."
About SUPERLOG
SUPERLOG is a unified system design language that provides a single environment for advanced design and verification methodologies. It encompasses all SOC methodology requirements -- from architectural specification through functional implementation, and complex verification.
SUPERLOG is a superset of the Verilog Hardware Description Language (HDL) IEEE 1364 standard and encompasses a large portion of the C Software Programming Language. Additional language constructs targeted at system modeling and verification provide a new level of descriptive power to dramatically improve productivity. Built to unify disparate parts of the design flow using the principle of a single language driving all design activities, SUPERLOG eliminates tool and methodology bottlenecks and streamlines the product development process.
For details about SUPERLOG, contact Dave Kelf, vice president of marketing at Co-Design. He can be reached via email at davek@co-design.com or at (617) 571-9883.
About VOLARE
Get2Chip's SOC multi-level synthesis platform, VOLARE, is the first comprehensive synthesis tool suite to rapidly perform system-level synthesis across a full chip via a top-down methodology. VOLARE extends today's design methodology from the register-transfer level to the architectural level. It is the first implementation tool to support a system-level design methodology, where full-chip, architectural synthesis and timing analysis are performed on blocks that may be described at the behavioral, register-transfer, and/or gate levels. VOLARE is ideally suited as a development platform for the emerging wireless, networking, telecom, and multimedia segments of the electronic design market. The tool runs on the Sun Solaris and Linux operating systems with a Java front-end.
About Co-Design Automation
Co-Design Automation is an electronic design automation (EDA) company focused on the efficient creation, implementation, and verification of system on chip (SOC) designs. Founded in 1997, it is privately held and funded by investors from within the EDA developer and user communities. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL, and Peter Flake, creator of the HILO HDL. In 1999, it announced the SUPERLOG system design language, now utilized by 12 partner companies. Its products --SYSTEMSIM and SYSTEMEX -- were unveiled in 2000 and are achieving success throughout the worldwide electronics industry. Corporate headquarters is in San Jose, Calif. Telephone: (877) 6 CODESIGN. Facsimile: (408) 273-6025. Email: info@co-design.com. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.
About Get2Chip
Get2Chip.com, Inc. was launched in early 2000 by semiconductor veterans and chip design tool experts from LSI Logic, VLSI Technology, Synopsys (NASDAQ: SNPS), and Mentor Graphics, among others. Get2Chip's breakthrough front-end tool suite, VOLARE, provides a fully integrated, multi-level synthesis technology, which offers the flexibility to do chip designs at the architectural-level, at the register-transfer-level (RTL) or at the gate-level. VOLARE, has been developed for complex SOC designs in ultra-deep sub-micron silicon technology, targeted towards wireless communication and multi-media applications. Get2Chip is privately held and its technology portfolio incorporates the synthesis technology originally developed under the name Meropa, Inc. Get2Chip has development centers in San Jose, Calif. and Munich, Germany. More information on Get2Chip, its products and services can be found at www.Get2Chip.com.
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VOLARE is a trademark of Get2Chip.com, Inc. SUPERLOG is a trademark of Co-Design Automation, Inc. Get2Chip.com acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
SYSTEMSIM, SYSTEMEX, CBlend and SUPERLOG are trademarks of Co-Design Automation, Inc. Verilog is a trademark of Cadence Design Systems, Inc. Co-Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
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